Arithmetic Micro-Operations

Question #1: The NAND or NOR gates are referred to as “universal” gates because:

Question #2: A correct output is achieved from a master-slave JK flip-flop only if its inputs are stable while the

Question #3: An inverter circuit can be realized with how many NAND gates:

Question #4: A modulus-12 ring counter requires a minimum of

Question #5: How is a strobe signal used when serially loading a shift register?

Question #6: An active-HIGH SR latch has a 0 on the S input and a 1 on the R input. Now when the R input goes to 0, the latch will be ________.

Question #7: The NAND or NOR gates are referred to as “universal” gates because:

Question #8: A sequential circuit gives an output depending upon:

Question #9: Synchronization is achieved by a timing device called a ________.

Question #10: Which of the following statements is false?

Question #11: The dual of any Boolean expression is obtained by:

Question #12: A Boolean operator ⊕ is defined as follows: 1 ⊕ 1 = 1, 1 ⊕ 0 = 0, 0 ⊕ 1 = 0 and 0 ⊕ 0 = 1 What will be the truth value of the expression (x ⊕ y) ⊕ z = x ⊕ (y ⊕ z)?

Question #13: How many different Boolean functions of degree 4 are there?

Question #14: A complete microcomputer system contains:

Question #15: Booth’s coding in 8-bits for the decimal number −57 is

Question #16: The 2’ complement representation of the decimal value −15 is

Question #17: Assuming all numbers are in 2’s complement representation, which of the following numbers is divisible by 11111011?

Question #18: Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is

Question #19: What is the minimum number of states required in the state transition graph of the above circuit?

Question #20: In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in:

Question #21: The principle of locality is used in:

Question #22: Which memory unit has lowest access time?

Question #23: During DMA transfer, the DMA controller takes over the buses to manage the transfer:

Question #24: Booth’s algorithm is used for the arithmetic operation of:

Question #25: The reason for improvement in CPU performance during pipe lining is:

Question #26: Use of cache memory enhances?

Question #27: An instruction cycle refers to

Question #28: A hardware interrupt is also called

Question #29: By applying the principle of temporal locality, processes are likely to reference pages that……………..

Question #30: Which of the following is a correct statement related to L2 cache memory?

Question #31: Priority is provided by———- for access to memory by various I/O channels and processors.

Question #32: What is the control unit’s function in the CPU?

Question #33: CPU fetches the data and instructions from………….

Question #34: Which of the following affects the processing power of the CPU?

Question #35: An N-bit carry look-ahead adder, where N is a multiple of 4, employs ICS 74181 (40-bit ALU) and 74182 (4-bit carry look-ahead generator). The minimum addition time using the best architecture for adder is:

Question #36: Which of the following is/are advantage of virtual memory?

Question #37: The number of full and half adders required to add 16-bit numbers is:

Question #38: Which of the following requires a device driver:

Question #39: More than one word are put in one cache block to:

Question #40: Which of the following statements is false?

Question #41: The total size of address space in a virtual memory system is limited by:

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