Computer Arithmetic Micro-Operations May 15, 2018 papertest 0 Comments arithmetic micro operations, arithmetic micro operations in computer architecture, arithmetic micro operations in computer organization arithmetic micro operations in co, arithmetic micro operations in computer organization ppt, explain all arithmetic micro operations, what are arithmetic micro operations Question #1: The NAND or NOR gates are referred to as “universal” gates because: they are easier to implement. they can be used to build all the other types of gates. they are available in different IC families. they are available everywhere in the world. Question #2: A correct output is achieved from a master-slave JK flip-flop only if its inputs are stable while the Clock is LOW lave is ready to receive the input from master Master gives a reset signal to slave Clock is HIGH Question #3: An inverter circuit can be realized with how many NAND gates: 1 2 3 None of these Question #4: A modulus-12 ring counter requires a minimum of 10 flip-flops 12 flip-flops 8 flip-flops None of these Question #5: How is a strobe signal used when serially loading a shift register? To turn the register set and reset To control the number of clocks To determine which output has a HIGH value To cascade it with other shift register Question #6: An active-HIGH SR latch has a 0 on the S input and a 1 on the R input. Now when the R input goes to 0, the latch will be ________. SET CLR STROBE RESET Question #7: The NAND or NOR gates are referred to as “universal” gates because: they are easier to implement. they can be used to build all the other types of gates. none of these hey are available in different IC families. Question #8: A sequential circuit gives an output depending upon: its present state inputs only. its present-1 state input only. both present- and past-state input. None of these Question #9: Synchronization is achieved by a timing device called a ________. Strobe Reset CLK Master clock generator Question #10: Which of the following statements is false? The 2’s complement of 0 is 0. In 2’s complement, the leftmost bit cannot be used to express a quantity. For an n-bit word (2’s complement) which includes the sign bit, there are 2n - 1 positive integers, 2n + 1 negative integers and one 0 for a total of 2n unique states. In 2’s complement, the significant information is contained in the 1’s of positive numbers and 0’s of the negative numbers. Question #11: The dual of any Boolean expression is obtained by: Interchanging POS and SOP terms Interchanging 0’s and 1’s Interchanging Boolean sums and Boolean products and also interchanging 0’s and 1’s Interchanging Boolean sums and Boolean products Question #12: A Boolean operator ⊕ is defined as follows: 1 ⊕ 1 = 1, 1 ⊕ 0 = 0, 0 ⊕ 1 = 0 and 0 ⊕ 0 = 1 What will be the truth value of the expression (x ⊕ y) ⊕ z = x ⊕ (y ⊕ z)? Cannot be defined, as ⊕ is defined for two inputs. Always true. Always false. True when any one of the inputs is true. Question #13: How many different Boolean functions of degree 4 are there? 2 4 2 8 2 12 2 16 Question #14: A complete microcomputer system contains: Microprocessor Memory I/O device All of the above Question #15: Booth’s coding in 8-bits for the decimal number −57 is 0 - 100 + 1000 0 − 1 + 100 - 10 + 1 00 − 10 + 100 − 1 0 − 100 + 100 − 1 Question #16: The 2’ complement representation of the decimal value −15 is 1111 11111 111111 10001 Question #17: Assuming all numbers are in 2’s complement representation, which of the following numbers is divisible by 11111011? 11100111 11100100 11010111 11011011 Question #18: Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is Θ(1) Θ(log n) Θ(n) Θ(n 2 ) Question #19: What is the minimum number of states required in the state transition graph of the above circuit? Question #20: In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in: Q = 0, Q′ = 1 Q = 1, Q′ = 0 Q = 1, Q′ = 1 Indeterminate states Question #21: The principle of locality is used in: Interrupt Registers DMA Cache memory Question #22: Which memory unit has lowest access time? Cache Registers Optical disk Main memory Question #23: During DMA transfer, the DMA controller takes over the buses to manage the transfer: Directly from CPU to memory. Directly from memory to CPU. Directly between the memory and registers Directly between the I/O device and memory Question #24: Booth’s algorithm is used for the arithmetic operation of: addition. subtraction. multiplication. division. Question #25: The reason for improvement in CPU performance during pipe lining is: educed memory access time. increased clock speed. introduction of parallelism. increase in cache memory. Question #26: Use of cache memory enhances? I/O access time memory access time. effective memory access time. secondary storage access time. Question #27: An instruction cycle refers to fetching an instruction. executing an instruction. fetching, decoding and executing an instruction. reading and executing an instruction. Question #28: A hardware interrupt is also called an internal interrupt. an external interrupt. a processor interrupt. a clock interrupt. Question #29: By applying the principle of temporal locality, processes are likely to reference pages that…………….. have been referenced recently. are located at address near recently referenced pages in memory. have been preloaded into memory. None of these Question #30: Which of the following is a correct statement related to L2 cache memory? The level 1 cache is always faster than the level 2 cache. The level 2 cache is used to mitigate the dynamic slowdown every time a level 1 cache miss occurs. none of these Level 2 cache comes as on board only. Question #31: Priority is provided by———- for access to memory by various I/O channels and processors. a register a counter the processor scheduler a controller Question #32: What is the control unit’s function in the CPU? To decode program instructions To transfer data to primary storage To perform logical operations To store arithmetic operations Question #33: CPU fetches the data and instructions from…………. ROM control unit RAM None of these Question #34: Which of the following affects the processing power of the CPU? Data bus, addressing schemes Clock speed, addressing schemes Clock speed, data bus Clock speed, data bus, addressing schemes Question #35: An N-bit carry look-ahead adder, where N is a multiple of 4, employs ICS 74181 (40-bit ALU) and 74182 (4-bit carry look-ahead generator). The minimum addition time using the best architecture for adder is: None of these Proportional to log N Proportional to log N A constant Question #36: Which of the following is/are advantage of virtual memory? Faster memory to memory on an average Processes can be given protected address spaces Linker can assign addresses independent of where the program will be loaded in physical memory. Programs larger than the physical memory size can be run Question #37: The number of full and half adders required to add 16-bit numbers is: 8 half adders, 8 full adders 1 half adder, 15 full adders 16 half adders, 0 full adder 4 half adders, 12 full adders Question #38: Which of the following requires a device driver: Register Cache Main memory Disk Question #39: More than one word are put in one cache block to: exploit the temporal locality of reference in a program. exploit the spatial locality of reference in a program. reduce the miss penalty. None of these Question #40: Which of the following statements is false? Virtual memory implements the translation of a program’s address space into physical memory address space. Virtual memory allows each program to exceed the size of the primary memory. Virtual memory increases the degree of multiprogramming. Virtual memory reduces the context-switching overhead. Question #41: The total size of address space in a virtual memory system is limited by: the length of MAR. the available secondary storage. the available main memory. None of these Congratulations, you passed! I'm sorry but you did not achieve the required score.